TY  - JOUR

T1  - Low area memory-free FPGA implementation of the AES algorithm

JO  - Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012

PY  - 2012/01/01

AU  - Chu J

AU  - Benaissa M

ED  - 

DO  - DOI: 10.1109/FPL.2012.6339250

SP  - 623

EP  - 626

Y2  - 2024/12/25

ER  -